1. Field of the Invention
The present invention relates generally to conductive structures for electrically conductive pads of a circuit board and fabrication method thereof, and more particularly to a fabrication method of different conductive structures for electrically conductive pads on surface of a circuit board for different electronic component connections.
2. Description of Related Art
In a flip chip package, a plurality of electrode pads is disposed on surface of an IC chip and a plurality of solder bumps is formed on the electrode pads. Corresponding to the electrode pads and the solder bumps, a plurality of electrically conductive pads and solder bumps is formed on an organic circuit board such that the IC chip can be disposed on the packaging substrate with its active surface facing down.
Due to increasing demands for electronic products having high speed, high functionality and small size, application field of the flip chip technology is increasing. Meanwhile, in order to further improve electrical performance of the electronic products, passive components such as resistors, capacitors and inductors become necessary in a flip chip package. The passive components are generally disposed on the circuit board by surface mounting technology. As a result, solder bumps and surface mounting component conductive structures exist on the circuit board at the same time. Materials of forming the solder bumps and the surface mounting component conductive structures are designed to be different in height and size so as to match different kinds of electronic components.
The industry usually uses chemical deposition and stencil printing technology to form solder materials on a circuit board.
FIGS. 1A to 1E show a conventional method of forming different conductive structures for electrically conductive pads of a circuit board. As shown in FIG. 1A, an organic insulating protection layer 21 is formed on a circuit board 20 having a plurality of electrically conductive pads 201, and then patterned so as to form a plurality of openings 211 for exposing the electrically conductive pads 201. As shown in FIG. 1B, a metal adhesion layer 22 is formed in the openings 211 on the electrically conductive pads 201 by sputtering, evaporation or electroless plating (or called chemical deposition). As shown in FIGS. 1C and 1D, a stencil 23 having grids 23a is used to form solder materials 24 on part of the metal adhesion layer 22 on the electrically conductive pads 201 of the circuit board 20. As shown in FIG. 1E, solder bumps 24′ are formed by reflowing the solder materials 24. Thus, the metal adhesion layer and solder bumps made of different material are formed on the electrically conductive pads 201 for different component connections.
However, in the stencil printing process, the higher the solder materials, the more difficult it is to control the height of solder bumps or solder balls in subsequent process. Thereby, solder bumps or solder balls of uneven heights are formed in the reflow process, which adversely affects the electrical connection between the chip and the circuit board. Meanwhile, the stencil printing method can easily cause too much solder material to be melted in the reflow process, which thus leads to bridge phenomenon (solder materials joined together at neighboring electrically conductive pads) and short circuit problem. In addition, it is difficult to provide fine pitch electrically conductive pads through such a method. Moreover, the use of too much solder material is not good for environment.